Referring to FIG. 1A of the drawings, the reference numeral 100 generally designates a conventional SAR ADC. ADC 100 generally comprises a capacitive digital-to-analog converter (CDAC) 102, a comparator 104, and SAR logic 106. In operation, the CDAC 102 receives an analog input signal AIN and a reference voltage REF, and by use of a binary search algorithm, SAR logic 106 uses comparison results from the comparator 104 to switch the CDAC 104 to resolve the voltage level of the analog input signal AIN to generate a digital output signal DOUT.
Turning to FIG. 1B, a flowchart 150 depicting a conventional binary search algorithm for ADC 100 can be seen. Initially, for the first iteration or clock cycle (i=1), the SAR logic 106 sets the CDAC voltage VDAC is set to one-half (½) of a reference voltage REF in step 152. The difference between the CDAC voltage VDAC and the analog input signals AIN (which has been sampled) is compared to an offset voltage in step 154. If the difference of the CDAC voltage VDAC and analog input signal AIN is greater than the offset voltage, then the CDAC voltage VDAC is decremented by (½)2 for the first iteration (i=1) in step 156; otherwise, the CDAC voltage VDAC is incremented by (½)2 for the first iteration (i=1) in step 158. The iteration is increased in step 160, and the process (beginning at step 154) is repeated. This process continues until resolution of the analog input signal AIN is achieved with a predetermined accuracy or resolution.
With this type of configuration, though, there are several drawbacks. For example, there is no error margin in the comparison, resulting in a slow resolution of the analog input signal AIN. Additionally, the CDAC 102 is switched at every cycle (for all i's), even though the CDAC voltage VCDAC is close to the analog input voltage AIN. Thus, there is a need for an improved SAR ADC.
Some other examples of conventional circuits are: U.S. Pat. Nos. 6,747,589; 5,017,920; 5,070,332; 6,611,222; 7,071,862; 7,432,844; U.S. Patent Pre-Grant Publ. No. 2008/0129573; Rengachari et al., “A 10-Bit Algorithmic A/D Converter for Cytosensor Application,” Proc. IEEE International Symposium on Circuits and Systems, 2005 (ISCAS 2005), vol. 6, pp. 6186-6189, May 23-26, 2005; and Sharma et al., “Research on Electronic Cytosensors Progress report for 2003,” Department of Electrical & Computer Science, Oregon State University, Nov. 26, 2003.